1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to methods for arranging a memory array, and methods for controlling the memory array.
2. Description of the Related Art
A memory cell in a dynamic random-access memory (DRAM) is formed of a capacitor that stores information as an electrical charge and a transistor that is used as a selector switch disposed between the capacitor and a bit line. In a conventional memory array of a folded bit line scheme, the minimum size of the memory cell is 8 F2, that is, 2 F in a bit line direction multiplied by 4 F in a word line direction, and the memory cell has a 1:2 shape in terms of the aspect ratio of the bit line direction to the word line direction. A character F in this case refers to the minimum process dimension and is expressed as ½ of a bit line pitch or a word line pitch, which is smaller one of the bit line pitch and the word line pitch. Conventionally, DRAMs having memory cells of the 1:2 shape have increased in capacity, from 4 Mbytes, 16 Mbytes, to 64 Mbytes, by a factor of four for each generation. These capacities, if expressed as 4 Mbytes=222, 16 Mbytes=224, and 64 Mbytes=226, respectively, in the format of a factorial of 2, have all been even powers of 2, that is, 22n (n: natural number). Since the memory cells themselves take the 1:2 shape in terms of aspect ratio, if the memory cells of a DRAM chip with a capacity of 22m are formed, the entire DRAM chip including memory arrays take the 1:2 shape, as shown in FIG. 45B. Accordingly, the 1:2 shape has been maintainable to obtain a capacity four times as large as that of the predecessor on a generation basis by finer-structuring.
The slowdown of the finer-structuring which has supported development of larger-capacity memory chips has come to reduce the development pace of these memory chips. At the same time, DRAMs improved in capacity by twice, that is, odd powers of 2, for each generation have come to be developed, and 128 Mbytes and 512 Mbytes are examples of such DRAMs. Memory chips with these capacities, unlike the above-mentioned chips of the even powers of 2, each have 22n+1 memory cells arranged, so 128 Mbyte and 512 Mbyte memory chips have a 1:1 or 1:4 shape, as shown in FIGS. 48A and 48B. It is desirable that the capacity of a DRAM chip be increased without changing the external geometry of its package so that the capacity per dual-inline memory module (DIMM) can be increased and so that the number of memory cells mounted can be maintained.
However, since memory chips with a capacity of an even power of 2 have a 1:1 or 1:4 shape, these chips become twice as great as the conventional ones of the 1:2 shape in terms of short-side or long-side length. Accordingly, use of the most advanced processes causes package to be oversized in short-side or long-side length, and hence, difficulty in enclosing DRAM chips in a package that contains DRAM chips which are one generation older. In addition, if the miniaturization of processes is accelerated to a level that allows chip to be enclosed in the package, chips that are twice or more in capacity will be enclosable.
FIGS. 48A and 48B show examples of the layout of memory blocks in a memory chip similar to that whose memory blocks are arranged to obtain a capacity of an even power of 2. In these examples, as discussed above, the chip has a 1:1 shape in terms of the aspect ratio as shown in FIG. 48A, or a 1:4 shape as shown in FIG. 48B. The chip has the same capacity as a chip having a short-side or long-side length twice as long as that of the abovementioned chip, thus becoming difficult to package.
In contrast to the above, FIG. 47 shows a chip split into 3×3 regions with a peripheral circuit region disposed centrally therein and a memory block in each of the remaining eight regions around the peripheral circuit region in order to obtain a 1:2 chip shape (refer to Japanese Laid-Open Patent Application Publication No. Hei 11-145420 for further details). In this configuration, the chip has the peripheral circuit region concentratedly disposed centrally therein. Since the area of the peripheral circuit region is determined by the total area of the surrounding memory cell blocks, if the number of circuit elements in the peripheral circuit region is too small, an unnecessary region is included, whereas if the number of circuit elements is too much, not all of elements can be arranged in the central region of the chip and thus the need arises for part of the elements to be arranged between memory blocks. Since pads are also arranged concentratedly in the central region, when the chip is packaged, lead frame wiring and bonding wires to the package pins will be concentrated, resulting in complex wiring.